module tb_addr_unit();
  
  reg clk, rst_n, enable;
  wire ready;
  
  wire [1:0] bank0, bank1, angle;
  wire c1, c2;
  
  addr_unit ADDR_UNIT
  (
    .addr_bank0 ( bank0  ),
    .addr_bank1 ( bank1  ),
    .addr_angle ( angle  ),
    .ready      ( ready  ),
    .exc_sel0   ( c1     ),
    .exc_sel1   ( c2     ),
    .enable     ( enable ),
    .clk        ( clk    ),
    .rst_n      ( rst_n  )
  );
  

  initial
    begin
      clk = 0;
      rst_n = 0;
      enable = 0;
      #50;
      rst_n = 1;
      #10
      enable = 1;
      @(posedge ready);
      enable = 0;
      #50
      enable = 1;
    end
  always #10
    clk = ~clk;
endmodule

